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? semiconductor msm63p238 1/28 general description the msm63p238 is a cmos 4-bit microcontroller with a built-in pocsag (post office code standardization advisory group) decoder, which employs oki's original nx-4/250 cpu core. the msm63p238 is a one-time-programmable rom-version product having one-time prom (otp) as internal program memory. the specifications of the msm63p238 are equal to those of the msm63238 except for electrical characteristics, packaging (only 80-pin flat package is available for the msm63p238), and some functions. features the features of the msm63p238 with an asterisk (*) differ from those of the mask rom-version msm63238. ? rich instruction set 439 instructions transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, rom table reference, external memory transfer, stack operations, flag operations, branch, conditional branch, call/return, control. ? rich selection of addressing modes indirect addressing of four data memory types, with current bank register, extra bank register, hl register and xy register. data memory bank internal direct addressing mode. ? processing speed two clocks per machine cycle, with most instructions executed in one machine cycle. minimum instruction execution time : 61 m s (@ 32.768 khz system clock) 1 m s (@ 2 mhz system clock) ? clock generation circuit low-speed clock : 32.768 khz/38.4 khz/76.8 khz crystal oscillator high-speed clock : 2 mhz (max.) rc or ceramic oscillator select ? program memory (prom) space* 16k words basic instruction length is 16 bits/1 word ? data memory space 1k nibbles ? external data memory space 64 kbytes (expandable by using an i/o port) ? semiconductor msm63p238 4-bit microcontroller with built-in 16k word prom, pocsag decoder, and melody circuit e2e0041-18-95 this version: sep. 1998
? semiconductor msm63p238 2/28 ? stack level call stack level : 16 levels register stack level : 16 levels ? pocsag decoder data rate : 512 bps/1200 bps/2400 bps user frame : 3 types user address : 6 types battery saving mode (for controlling intermittent operations of rf receiver) ? i/o ports input ports: selectable as input with pull-up resistance/input with pull-down resistance/ high-impedance input output ports: selectable as p-channel open drain output/n-channel open drain output/ cmos output/high-impedance output input-output ports: selectable as input with pull-up resistance/input with pull-down resistance/high-impedance input selectable as p-channel open drain output/n-channel open drain output/cmos output/high-impedance output can be interfaced with external peripherals that use a different power supply than this device uses. number of ports: input port : 1 port 4 bits output port : 6 ports 4 bits input-output port : 5 ports 4 bits 1 port 2 bits ? melody output function melody sound frequency : 529 to 2979 hz tone length : 63 types tempo : 15 types note data : resides in the program memory buzzer drive signal output : 4 khz ? reset function reset through reset pin power-on reset reset by low-speed oscillation halt ? battery check* low-voltage supply check criterion voltage : can be selected as 2.20 0.20 v or 2.80 0.30 v ? power supply backup* backup circuit (voltage multiplier) enables operation at 1.45 v minimum
? semiconductor msm63p238 3/28 ? timers and counter 8-bit timer 4 selectable as auto-reload mode/capture mode/clock frequency measurement mode watchdog timer 1 15-bit time base counter 1 1, 2, 4, 8, 16, 32, 64, and 128 hz signals can be read ? serial port mode : uart mode, synchronous mode uart communication speed : 1200 bps, 2400 bps, 4800 bps, 9600 bps clock frequency in synchronous mode : 32.768 khz (internal clock mode), external clock frequency data length : 5 to 8 bits ? interrupt sources external interrupt : 3 internal interrupt : 15 (w atchdog timer interrupt is a nonmask- able interrupt) ? operating voltage* when backup used : v dd = 1.45 to 2.7 v when backup not used : v dd = 2.7 to 5.5 v ? package*: 80-pin plastic qfp (qfp80-p-1420-0.80-bk) : (product name: MSM63P238-XXXGS-BK) xxx indicates a code number.
? semiconductor msm63p238 4/28 block diagram an asterisk (*) indicates the port secondary function. and indicate that the power is supplied from v ddi to the circuits corresponding to the signal names inside , and from v ddr to the circuits corresponding to signal names inside . (v ddi and v ddr : power supply for interface) prom 16kw extmem bus con- trol mie xtm0 xtm1 xt0 xt1 osc0 osc1 tbcclk * hsclk * reset osc cbr ebr l c g z alu ra a ir instruction decoder ram 1024n d0-7 * a0-15 * rd * wr * nx-4/250 melody md i/o port p8.0, p8.1 p9.0-p9.3 pa.0-pa.3 pb.0-pb.3 pc.0-pc.3 pd.0-pd.3 rst tst1 tst tst2 v ddi 3 int pc h y x timing con- trol sp rsp stack cal.s: 16-level reg.s: 16-level int timer 8bit 4 rxc * txc* rxd * txd * 4 int sio tm0cap/tm1cap * tm0ovf/tm1ovf * t02ck * t13ck * 2 int 1 int tst3 xtsel0 xtsel1 v ddh v dd v ddl v dd2 cb1 cb2 backup p0.0-p0.3 p8.2, p8.3 pe.0-pe.3 pf.0-pf.3 internal port pocsag dec input port p1.0-p1.3 p7.0-p7.3 p6.0-p6.3 p5.0-p5.3 p4.0-p4.3 p3.0-p3.3 p2.0-p2.3 1 int output port data bus tbc 4 int bld wdt 1 int 3 int sigin bs1 bs2 v ddr v pp
? semiconductor msm63p238 5/28 pin configuration (top view) 80-pin plastic qfp note: pins marked as (nc) are no-connection pins which are left open. (nc) 41 pc.0 42 pc.1 43 pc.2 44 pc.3 45 pb.0 46 pb.1 47 pb.2 48 pb.3 49 p1.0 50 p1.1 51 p1.2 52 p1.3 53 p2.0 54 p2.1 55 p2.2 56 p2.3 57 p3.0 58 p3.1 59 p3.2 60 p3.3 61 p8.0 62 (nc) 63 p8.1 64 pd.3 40 pd.2 39 pd.1 38 pd.0 37 v ddi 36 v pp 35 reset 34 md 33 v ss 32 v dd 31 cb2 30 cb1 29 v ddh 28 v ddl 27 v dd2 26 (nc) 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 xtm1 xtm0 xtsel1 xtsel0 osc1 osc0 tst3 tst2 tst1 xt1 xt0 v ddr sigin bs2 bs1 p7.3 p7.2 p7.1 p7.0 p6.3 p6.2 p6.1 p6.0 (nc) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p9.0 p9.1 p9.2 p9.3 pa.0 pa.1 pa.2 pa.3 p4.0 p4.1 p4.2 p4.3 p5.0 p5.1 p5.2 p5.3
? semiconductor msm63p238 6/28 pin descriptions the basic functions of each pin of the msm63p238 are described in table 1. a symbol with a slash (/) denotes a pin that has a secondary function. refer to table 2 for secondary functions. for type, "" denotes a power supply pin, "i" an input pin, "o" an output pin, and "i/o" an input- output pin. table 1 pin descriptions (basic functions) function symbol type description v dd positive power supply v ss negative power supply v ddr interface power supply for sigin, bs1, bs2 v ddi positive power supply pin for external interface (power supply for input, output, and i/o ports) v ddl positive power supply pin for internal logic (internally generated). a capacitor (0.1 m f) should be connected between this pin and v ss . v ddh voltage multiplier pin for power supply backup (internally generated). a capacitor (1.0 m f) should be connected between this pin and v ss . cb1 pins to connect a capacitor for voltage multiplier. a capacitor (1.0 m f) should be connected between cb1 and cb2. cb2 xt0 i clock oscillation pins for pocsag decoder. a 32.768 khz, 38.4 khz, or 76.8 khz crystal and capacitor (c g ) should be connected to these pins. xt1 o xtm0 i xtm1 o osc0 i high-speed clock oscillation pins. a ceramic resonator and capacitors (c l0 , c l1 ) or external oscillation resistor (r os ) should be connected to these pins. osc1 o xtsel0 i low-speed cpu clock select pins. these pins are used to select a low-speed cpu clock. because these are high impedance inputs, be sure to tie these pins to v dd or v ss . xtsel1 tst1 input pins for testing. pull-down resistors are internally connected to these pins. the user cannot use these pins. tst2 i tst3 reset i reset input pin. setting this pin to "h" level puts this device into a reset state. t hen, setting this pin to "l" level starts executing an instruction from address 0000h. a pull-down resistor is internally connected to this pin. low-speed clock oscillation pins for cpu. a 32.768 khz crystal and capacitor (c gm ) should be connected to these pins. power supply oscillation test reset v dd2 positive power supply pin for low-speed clock (internally generated) 31 32 13 36 27 26 28 29 30 14 15 23 24 19 20 21 22 16 17 18 34 pin v pp power supply (+12.5 v) for prom writing 35
? semiconductor msm63p238 7/28 table 1 pin descriptions (basic functions) (continued) function symbol type description md o melody output pin (normal phase) bs1 o battery saving outputs. signals to control intermittent operations of rf receiver. bs2 sigin i receive data input pin. input pin for receive data from rf receiver. melody pocsag decoder 33 10 11 12 pin p1.0/int5 50 p1.1/int5 51 p1.2/int5 52 p1.3/int5 53 i 4-bit input port. pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. p2.0 54 p2.1 55 p2.2 56 p2.3 57 p3.0 58 p3.1 59 p3.2 60 p3.3 61 p4.0/a0 73 p4.1/a1 74 p4.2/a2 75 p4.3/a3 76 p5.0/a4 77 p5.1/a5 78 p5.2/a6 79 p5.3/a7 80 p6.0/a8 2 p6.1/a9 3 p6.2/a10 4 p6.3/a11 5 p7.0/a12 6 p7.1/a13 7 p7.2/a14 8 p7.3/a15 9 o port 4-bit output ports. p-channel open drain output, n-channel open drain output, cmos output, or high-impedance output is selectable for each bit. o o o o o
? semiconductor msm63p238 8/28 table 1 pin descriptions (basic functions) (continued) function symbol type description pin p8.0/ rd 62 p8.1/ wr 64 p9.0/d0 65 p9.1/d1 66 p9.2/d2 67 p9.3/d3 68 pa.0/d4 69 pa.1/d5 70 pa.2/d6 71 pa.3/d7 72 pb.0/int0/ tm0cap/ tm0ovf 46 pb.1/int0/ tm1cap/ tm1ovf 47 pb.2/int0/ t02ck 48 pb.3/int0/ t13ck 49 pc.0/int1/ rxd 42 i/o port 2-bit input-output port and 4-bit input-output ports. in input mode, pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. in output mode, p-channel open drain output, n-channel open drain output, cmos output, or high-impedance output is selectable for each bit. pc.1/int1/ txc 43 pc.2/int1/ rxc 44 pc.3/int1/ txd 45 pd.0 37 pd.1 38 pd.2 39 pd.3 40 i/o i/o i/o i/o i/o
? semiconductor msm63p238 9/28 table 2 shows the secondary functions of each pin of the msm63p238. table 2 pin descriptions (secondary functions) function symbol type description pin pb.0/int0 46 capture external 0 interrupt input pins. the change of input signal level causes an interrupt to occur. the port b interrupt enable register (pbie) enables or disables an interrupt for each bit. pb.1/int0 47 pb.2/int0 48 pb.3/int0 49 i pc.0/int1 42 external 1 interrupt input pins. the change of input signal level causes an interrupt to occur. the port c interrupt enable register (pcie) enables or disables an interrupt for each bit. pc.1/int1 43 pc.2/int1 44 pc.3/int1 45 i p1.0/int5 50 external 5 interrupt input pins. the change of input signal level causes an interrupt to occur. the port 1 interrupt enable register (p1ie) enables or disables an interrupt for each bit. p1.1/int5 51 p1.2/int5 52 p1.3/int5 53 i pb.0/tm0cap 46 i timer 0 capture trigger input pin. pb.1/tm1cap 47 i timer 1 capture trigger input pin. external interrupt
? semiconductor msm63p238 10/28 table 2 pin descriptions (secondary functions) (continued) function symbol type description pin pb.0/tm0ovf 46 o timer 0 overflow flag output pin. pb.1/tm1ovf 47 o timer 1 overflow flag output pin. pb.2/t02ck 48 i external clock input pin for timer 0 and timer 2. pb.3/t13ck 49 i external clock input pin for timer 1 and timer 3. timer pd.2/tbcclk 39 o low-speed oscillation clock output pin pd.3/hsclk 40 o high-speed oscillation clock output pin oscillation output pc.0/rxd 42 i serial port receive data input pin sync serial port clock input-output pin. transmit clock output when this device is used as a master processor. transmit clock input when this device is used as a slave processor. pc.1/txc 43 i/o sync serial port clock input-output pin. receive clock output when this device is used as a master processor. receive clock input when this device is used as a slave processor. pc.2/rxc 44 i/o pc.3/txd 45 o serial port transmit data output pin. serial port
? semiconductor msm63p238 11/28 table 2 pin descriptions (secondary functions) (continued) function symbol type description pin p4.0/a0 73 address output bus for external memory external memory read signal output pin for external memory (negative logic) o p4.1/a1 74 p4.2/a2 75 p4.3/a3 76 p5.0/a4 77 p5.1/a5 78 p5.2/a6 79 p5.3/a7 80 p6.0/a8 2 p6.1/a9 3 p6.2/a10 4 p6.3/a11 5 p7.0/a12 6 p7.1/a13 7 p7.2/a14 8 p7.3/a15 9 p9.0/d0 65 p9.1/d1 66 p9.2/d2 67 p9.3/d3 68 pa.0/d4 69 pa.1/d5 70 pa.2/d6 71 pa.3/d7 72 p8.0/ rd 62 write signal output pin for external memory (negative logic) o p8.1/ wr 64 data bus for external memory i/o o
? semiconductor msm63p238 12/28 absolute maximum ratings parameter symbol condition rating unit power supply voltage 1 v dd backup used, ta = 25c C0.3 to +3.0 v power supply voltage 2 v ddi ta = 25c C0.3 to +6.0 v power supply voltage 3 v ddr ta = 25c C0.3 to +6.0 v power supply voltage 4 v ddh ta = 25c C0.3 to +6.0 v power supply voltage 5 v ddl ta = 25c C0.3 to +6.0 v input voltage 1 v in1 v dd input, ta = 25c C0.3 to v dd + 0.3 v input voltage 2 v in2 v ddi input, ta = 25c C0.3 to v ddi + 0.3 v output voltage 1 v in3 v ddr input, ta = 25c C0.3 to v ddr + 0.3 v output voltage 2 v out1 v dd output, ta = 25c C0.3 to v dd + 0.3 v output voltage 3 v out2 v ddi output, ta = 25c C0.3 to v ddi + 0.3 v output voltage 4 v out3 v ddr output, ta = 25c C0.3 to v ddr + 0.3 v storage temperature v out4 v ddh output, ta = 25c C0.3 to v ddh + 0.3 v C55 to +150 c input voltage 3 t stg (v ss = 0 v) backup not used, ta = 25c C0.3 to +6.0
? semiconductor msm63p238 13/28 recommended operating conditions ? when backup is used v ddi 1.45 to 5.5 v v ddr 1.45 to 5.5 v crystal oscillation frequency f xt 30 to 80 khz f xtm 30 to 35 khz ceramic oscillation frequency f cm 200k to 1m hz v dd = 1.45 to 2.7 v parameter symbol condition range unit operating temperature t op 0 to +65 c v dd 1.45 to 2.7 v operating voltage (v ss = 0 v) external rc oscillator resistance r os 50 to 300 k w v dd = 1.45 to 2.7 v v ddi 1.8 to 5.5 v v ddr 1.8 to 5.5 v crystal oscillation frequency f xt 30 to 80 khz f xtm 30 to 35 khz ceramic oscillation frequency f cm 300k to 1m hz v dd = 2.7 to 5.5 v parameter symbol condition range unit operating temperature t op 0 to +65 c v dd 2.7 to 5.5 v operating voltage (v ss = 0 v) external rc oscillator resistance r os 50 to 300 k w v dd = 2.7 to 5.5 v 200k to 2m v dd = 2.9 to 5.5 v 30 to 300 v dd = 2.9 to 5.5 v ? when backup is not used
? semiconductor msm63p238 14/28 electrical characteristics dc characteristics parameter symbol condition mea- suring circuit (v dd = v ddi = v ddr = 1.45 to 5.5 v, v ddh = 2.7 to 5.5 v, v ss = 0 v, ta = 0 to +65c unless otherwise specified) unit max. typ. min. 1 v ddl voltage v ddl high speed clock stop 1.2 1.6 2.0 v high speed clock oscillation 1.45 5.5 v crystal oscillation start voltage v sta oscillation start time: within 5 seconds 1.45 v crystal oscillation hold voltage v hold 1.45 v crystal oscillation stop detect time t stop 0.1 5.0 ms external crystal oscillator capacitance c g , c gm 12 30 pf internal crystal oscillator capacitance c d , c dm 12 15 20 pf internal rc oscillator capacitance por voltage non-por voltage c os 81216pf v por1 v dd = 1.5 v 0.0 0.4 v v por2 v dd = 1.5 v 1.45 1.5 v 2.7 3.0 v 0.0 0.7 v v dd = 3.0 v v dd = 3.0 v v dd2 voltage v dd2 1.2 2.0 v 1.6 notes: 1. "t stop " indicates that if the crystal oscillator stops over the value of t stop , the system reset occurs. 2. "por" denotes power on reset. 3. "v por1 " indicates that por occurs when v dd falls from v dd to v por1 and again rises up to v dd . 4. "v por2 " indicates that por does not occur when v dd falls from v dd to v por2 and again rises up to v dd .
? semiconductor msm63p238 15/28 dc characteristics (continued) ? when backup is used parameter symbol condition mea- suring circuit (v dd = v ddi = 1.5 v, v ddh = 3.0 v, v ss = 0 v, ta = 0 to +65c unless otherwise specified) unit max. typ. min. 35 7.0 supply current 1 i dd1 cpu in halt mode. m a 1 (high-speed clock oscillation stop) decoder in halt mode. (decoder oscillation stop) 40 17 supply current 2 i dd2 cpu in halt mode. m a (high-speed clock oscillation stop) decoder in carrier on state. (76.8 khz operation) 200 85 supply current 3 i dd3 cpu in halt mode. m a (high-speed clock oscillation stop) decoder in data receiving state. (76.8 khz operation) 400 230 supply current 4 i dd4 cpu in operation at 32 khz. m a (high-speed clock oscillation stop) decoder in halt mode. (decoder oscillation stop) 2.0 1.5 supply current 5 i dd5 cpu in operation at high speed. ma (rc oscillation, r os = 51 k w ) decoder in halt mode. (decoder oscillation stop) 3.0 2.0 supply current 6 i dd6 cpu in operation at high speed. ma (ceramic oscillation, 1 mhz) decoder in halt mode. (decoder oscillaiton stop)
? semiconductor msm63p238 16/28 dc characteristics (continued) ? when backup is not used parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = 3.0 v, v ss = 0 v, ta = 0 to +65c unless otherwise specified) unit max. typ. min. 20 3.0 supply current 1 i dd1 cpu in halt mode. m a 1 (high-speed clock oscillation stop) decoder in halt mode. (decoder oscillation stop) 20 8.0 supply current 2 i dd2 cpu in halt mode. m a (high-speed clock oscillation stop) decoder in carrier on state. (76.8 khz operation) 100 42 supply current 3 i dd3 cpu in halt mode. m a (high-speed clock oscillation stop) decoder in data receiving state. (76.8 khz operation) 200 120 supply current 4 i dd4 cpu in operation at 32 khz. m a (high-speed clock oscillation stop) decoder in halt mode. (decoder oscillation stop) 2.0 1.5 supply current 5 i dd5 cpu in operation at high speed. ma (rc oscillation, r os = 51 k w ) decoder in halt mode. (decoder oscillation stop) 5.0 3.5 supply current 6 i dd6 cpu in operation at high speed. ma (ceramic oscillation, 2 mhz) decoder in halt mode. (decoder oscillation stop)
? semiconductor msm63p238 17/28 dc characteristics (continued) parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = v ddr = 3.0 v, v ss = 0 v, ta = 0 to +65c unless otherwise specified) unit max. output current 1 (p2.0 to p2.3) (p3.0 to p3.3) (p4.0 to p4.3) (pc.0 to pc.3) (pd.0 to pd.3) C0.4 ma 2 i oh1 v oh1 = v ddi C 0.5 v C1.0 ma C2.0 ma output current 2 (md) output current 4 (osc1) i oh4r v oh4r = v ddh C 0.5 v (rc oscillation) C0.75 ma output leakage (p2.0 to p2.3) (p3.0 to p3.3) (p4.0 to p4.3) (pd.0 to pd.3) i ooh v oh = v ddi 1.0 m a i ool v ol = v ss m a . . . typ. C1.2 C3.0 C4.0 C1.5 min. C2.0 C5.0 C8.0 C2.5 C1.0 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v 2.0 ma i ol1 v ol1 = 0.5 v 5.0 ma 8.0 ma 1.4 3.0 4.0 0.4 1.0 2.0 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v C0.5 ma i oh2 v oh2 = v dd C 0.7 v C2.0 ma C4.0 ma C1.3 C4.0 C5.5 C2.5 C6.0 C9.0 v dd = 1.5 v v dd = 3.0 v v dd = v ddh = 5.0 v 2.5 ma i ol2 v ol2 = 0.7 v 6.0 ma 9.0 ma 1.3 4.0 5.5 0.5 2.0 4.0 v dd = 1.5 v v dd = 3.0 v v dd = v ddh = 5.0 v output current 3 (bs1, bs2) C1.2 ma i oh3 v oh3 = v ddr C 0.5 v C3.0 ma C6.0 ma C3.6 C9.0 C12.0 C6.0 C15.0 C24.0 v ddr = 1.5 v v ddr = 3.0 v v ddr = 5.0 v 6.0 ma i ol3 v ol3 = 0.5 v 15.0 ma 24.0 ma 3.6 9.0 12.0 1.2 3.0 6.0 v ddr = 1.5 v v ddr = 3.0 v v ddr = 5.0 v v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C1.0 ma C2.0 C3.0 i ol4r v ol4r = 0.5 v (rc oscillation) 2.5 ma 1.5 0.75 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v 3.5 ma 2.0 1.0 i oh4c v oh4c = v ddh C 0.5 v (ceramic oscillation) C60 m a C120 C240 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C100 m a C200 C400 i ol4c v ol4c = 0.5 v (ceramic oscillation) 250 m a 120 60 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v 400 m a 200 100 . . .
? semiconductor msm63p238 18/28 dc characteristics (continued) parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = v ddr = 3.0 v, v ss = 0 v, ta = 0 to +65c unless otherwise specified) unit max. input current 1 (p1.0 to p1.3) (p8.0, p8.1) (p9.0 to p9.3) (pd.0 to pd.3) 30 m a 3 i ih1 v ih1 = v ddi (when pulled down) 180 600 input current 2 (sigin) input current 4 (reset) i ih4 v ih4 = v dd 80 . . . typ. 10 90 250 50 min. 2 30 70 10 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v C2 i il1 v il1 = v ss (when pulled up) C30 C70 C10 C90 C250 C30 C180 C600 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v input current 3 (osc0) C30 i il3 v il3 = v ss (when pulled up) C150 C110 C350 C200 C600 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v v dd = 1.5 v v dd = 3.0 v 600 350 150 i ih1z v ih1 = v ddi (in a high impedance state) 1.0 0.0 i il1z v il1 = v ss (in a high impedance state) 0.0 C1.0 i ih2z v ih2 = v ddr 1.0 0.0 i il2z v il2 = v ss 0.0 C1.0 i ih3r v ih3 = v ddh (rc oscillation) 1.0 0.0 i il3r v il3 = v ss (rc oscillation) 0.0 C1.0 1.0 i ih3c v ih3 = v ddh (ceramic oscillation) 3.0 0.5 1.5 0.1 0.75 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C0.1 i il3c v il3 = v ss (ceramic oscillation) C0.75 C0.5 C1.5 C1.0 C3.0 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v v dd = v ddh = 5.0 v 2.0 ma 1.0 0.5 i il4 v il4 = v ss 0.0 m a C1.0 input current 5 (tst1, tst2, tst3) i ih5 v ih5 = v dd 300 m a 150 50 v dd = 1.5 v v dd = 3.0 v 1.5 ma 1.0 0.5 v dd = v ddh = 5.0 v 4.0 ma 2.5 1.25 i il5 v il5 = v ss 0.0 m a C1.0 i ih6z v ih6 = v dd 1.0 m a 0.0 input current 6 (xtsel0, xtsel1) i il6z v il6 = v ss 0.0 m a C1.0 m a m a m a m a m a m a m a m a m a m a m a m a m a m a m a m a m a m a m a
? semiconductor msm63p238 19/28 dc characteristics (continued) parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = v ddr = 3.0 v, v ss = 0 v, ta = 0 to +65c unless otherwise specified) unit max. typ. min. input voltage 1 (p1.0 to p1.3) (p8.0, p8.1) (p9.0 to p9.3) (pd.0 to pd.3) v ddi = 1.5 v 1.2 1.5 v 4 v ih1 v ddi = 3.0 v 2.4 3.0 v v ddi = 5.0 v 4.0 5.0 v input voltage 3 (osc0) . . . d v t2 input pin capacitance (p1.0 to p1.3) (p8.0, p8.1) (p9.0 to p9.3) (pd.0 to pd.3) c in 5pf hysteresis width 2 (reset, tst1, tst2, tst3, xtsel0, xtsel1) . . . 1 v ddi = 1.5 v 0.0 0.3 v v il1 v ddi = 3.0 v 0.0 0.6 v v ddi = 5.0 v 0.0 1.0 v input voltage 2 (sigin) v ddr = 1.5 v 1.2 1.5 v v ih2 v ddr = 3.0 v 2.4 3.0 v v ddr = 5.0 v 4.0 5.0 v v ddr = 1.5 v 0.0 0.3 v v il2 v ddr = 3.0 v 0.0 0.6 v v ddr = 5.0 v 0.0 1.0 v v dd = v ddh = 3.0 v 2.4 3.0 v v ih3 v dd = v ddh = 5.0 v 4.0 5.0 v v dd = v ddh = 3.0 v 0.0 0.6 v v il3 v dd = v ddh = 5.0 v 0.0 1.0 v input voltage 4 (reset, tst1, tst2, tst3, xtsel0, xtsel1) v dd = 1.5 v 1.35 1.5 v v ih4 v dd = 3.0 v 2.4 3.0 v v dd = v ddh = 5.0 v 4.0 5.0 v v dd = 1.5 v 0.0 0.15 v v il4 v dd = 3.0 v 0.0 0.6 v v dd = v ddh = 5.0 v 0.0 1.0 v v ddi = 1.5 v 0.05 0.1 0.3 v d v t1 v ddi = 3.0 v 0.2 0.5 1.0 v v ddi = 5.0 v 0.25 1.0 1.5 v hysteresis width 1 (p1.0 to p1.3) (p8.0, p8.1) (pd.0 to pd.3) . . . v dd = 1.5 v 0.05 0.1 0.3 v v dd = 3.0 v 0.2 0.5 1.0 v v dd = v ddh = 5.0 v 0.25 1.0 1.5 v
? semiconductor msm63p238 20/28 measuring circuit 1 measuring circuit 2 a v ss v dd v ddr v ddh v ddi c g xt0 xt1 cb1 cb2 osc0 osc1 q w (*1) c l0 c l1 q w q w r os *1 rc oscillator ceramic oscillator ceramic resonator c l , c 2 c h , c b12 c g , c gm c l0 c l1 ceramic resonator : 0.1 m f : 1 m f : 15 pf : 30 pf : 30 pf : csb1000j (1 mhz) csa2.00mg (2 mhz) (murata mfg.-make) v v c 2 v dd2 c gm xtm0 xtm1 c h c b12 v ddl v c l 76.8 khz crystal 32.768 khz crystal a (*3) v ss v dd v ddr v ddi (*2) v ih v il *2 input logic circuit to determine the specified measuring conditions. *3 measured at the s p ecified out p ut p ins. v ddh v dd2 v ddl output input
? semiconductor msm63p238 21/28 measuring circuit 3 measuring circuit 4 v ss v dd v ddr v ddl v ddi a v dd2 (*4) v ddh input output v ss v dd v ddr v ddl v ddi (*4) v ih v il *4 measured at the s p ecified in p ut p ins. v dd2 v ddh input output waveform monitoring
? semiconductor msm63p238 22/28 txd (pc.3) rxd (pc.0) t cyc t ddr t r t f t cwh t cwl t ddr t ds t ds t dh 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) txc (pc.1)/ rxc (pc.2) ac characteristics (serial interface, serial port) (v dd = v ddr = 1.45 to 5.5 v, v ddh = 2.7 to 5.5 v, v ss = 0 v, v ddi = 5.0 v, ta = 0 to +65 c unless otherwise specified) (1) synchronous communication parameter symbol condition unit txc/rxc input fall time max. typ. min. t f m s 1.0 txc/rxc input rise time t r m s 1.0 0.8 txc/rxc input "l" level pulse width t cwl m s 0.8 txc/rxc input "h" level pulse width t cwh m s 2.0 txc/rxc input cycle time t cyc m s txc/rxc output cycle time t cyc1(o) cpu in operation state at 32 khz m s 30.5 t cyc2(o) cpu in operation at 2 mhz v dd = v ddh = 2.9 v to 5.5 v m s 0.5 txd output delay time t ddr output load capacitance 10 pf m s 0.4 0.5 rxd input setup time t ds m s 0.8 rxd input hold time t dh m s synchronous communication timing ("h" level = 4.0 v, "l" level = 1.0 v)
? semiconductor msm63p238 23/28 txd (pc.3) t brt 5 v (v ddi ) 0 v (v ss ) rxd (pc.0) r brt 5 v (v ddi ) 0 v (v ss ) (2) uart communication parameter symbol condition unit t brt Ct cr transmit baud rate max. typ. min. t brt t brt = 1/f brt t cr = 1/f osc s t brt t brt +t cr r brt 0.97 receive baud rate r brt s r brt r brt 1.03 r brt = 1/f brt f brt : baud rates (1200, 2400, 4800, 9600 bps) uart communication timing ("h" level = 4.0 v, "l" level = 1.0 v)
? semiconductor msm63p238 24/28 ac characteristics (external memory interface) (v dd = v ddr = 1.45 to 5.5 v, v ddh = 2.7 to 5.5 v, v ss = 0 v, v ddi = 5.0 v, ta = 0 to +65 c unless otherwise specified) (1) reading from external memory parameter read cycle time rd output delay time output valid time external memory output delay time symbol condition min. typ. max. unit t rc t oe t oha t do 61.0 m s m s m s m s 5.0 5.0 5.0 (a) when cpu operates at 32.768 khz parameter read cycle time rd output delay time output valid time external memory output delay time symbol condition min. typ. max. unit t rc t oe t oha t do 1.0 m s ns ns ns 100 100 150 (b) when cpu operates at 2 mhz (v ddh = 2.9 to 5.5 v) ac characteristics timing ("h" level = 4.0 v, "l" level = 1.0 v) t rc t oe t oha t do address output port setup value port setup value input data port setup value port setup value p7 - p4 (a15 - a0) p8.0 ( rd ) pa, p9 (d7 - d0) movxb obj, [ra] movxb obj, xadr16 s2 s1 s2 s1 s2 s1 system clock 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss )
? semiconductor msm63p238 25/28 (2) writing to external memory parameter write cycle time address setup time write time write recovery time symbol condition min. typ. max. unit t wc t as t w t wr 61.0 m s m s m s m s (a) when cpu operates at 32.768 khz data setup time t ds m s data hold time t dh m s 30.5 15.3 15.3 45.8 15.3 parameter write cycle time address setup time write time write recovery time symbol condition min. typ. max. unit t wc t as t w t wr 1.0 m s m s m s m s (b) when cpu operates at 2 mhz (v ddh = 2.9 to 5.5 v) data setup time t ds m s data hold time t dh m s 0.4 0.2 0.2 0.7 0.2 ac characteristics timing ("h" level = 4.0 v, "l" level = 1.0 v) t wc t ds t dh t as address output port setup value port setup value p7 - p4 (a15 - a0) p8.1 ( wr ) pa, p9 (d7 - d0) movxb [ra], obj or movxb xadr16, obj s2 s1 s2 s1 s2 s1 system clock output data port setup value port setup value t w t wr 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss )
? semiconductor msm63p238 26/28 application circuits note: v ddi is the power supply pin for the input, output, and input-output ports. v ddr is the interface power supply pin for sigin, bs1, and bs2. be sure to connect the v ddi and v ddr pins either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with power supply backup xt0 xt1 xtm0 v dd cb1 cb2 v ddl reset tst1 tst2 v ss osc0 osc1 r os c b12 c v c gm 12 to 30 pf 1.5 v c l ? rc oscillation is selected as high-speed oscillation. ? ports and rf section are powered from external memory power source. ? c v is an ic power supply bypass capacitor. ? values of c l , c 2 , c g , c gm , c h , c b12 , and c v are for reference only. v ddi p4-7 p9, pa p8.0 p8.1 v dd a15-0 d7-0 rd wr v ss lcd module rom sram eeprom 5.0 v 76.8 khz crystal push sw msm63p238 p3 p2 pc pd key matrix led vibrator uart v dd v ss v dd v ss rf section tst3 xtsel1 xtsel0 xtm1 c h 32.768 khz crystal c g 12 to 30 pf v ddr sigin bs1 bs2 v dd2 c 2 v ddh 1.0 m f 0.1 m f 1.0 m f 0.1 m f 0.1 m f open external memory
? semiconductor msm63p238 27/28 note: v ddi is the power supply pin for the input, output, and input-output ports. v ddr is the interface power supply pin for sigin, bs1, and bs2. be sure to connect the v ddi and v ddr pins either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with no power supply backup xt0 xt1 xtm0 v dd cb1 cb2 reset tst1 tst2 v ss c v 3.0 v ? ceramic oscillation is selected as high-speed oscillation. ? ports and rf section are powered from external memory power source. ? c v is an ic power supply bypass capacitor. ? values of c l , c 2 , c g , c v , c l0 , and c l1 are for reference only. v ddi p4-7 p9, pa p8.0 p8.1 v dd a15-0 d7-0 rd wr v ss lcd module rom sram eeprom 32.768 khz crystal push sw msm63p238 p3 p2 pc pd key matrix led vibrator uart v dd v ss v dd v ss rf section tst3 xtsel1 xtsel0 xtm1 c 2 c g 12 to 30 pf osc0 osc1 c l0 c l1 ceramic resonator v ddr sigin bs1 bs2 v ddh c l v ddl v dd2 30 pf 0.1 m f 0.1 m f 0.1 m f open open 30 pf external memory application circuits (continued)
? semiconductor msm63p238 28/28 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. mirror finish package dimensions

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